Huawei board director and head of the semiconductor business unit He Tingbo, on May 26, at the IEEE Circuits and Systems International Symposium, unveiled the “Tau (τ) Scaling Law” and the “LogicFolding” chip architecture, claiming that it can achieve a 55% improvement in transistor density and a 41% improvement in power efficiency without relying on EUV extreme ultraviolet lithography equipment; the target is to reach a transistor density equivalent to a 1.4nm process by 2031.
Technical logic of the Tau scaling law: from geometric shrinking to time optimization
The core innovation of the Tau scaling law lies in a shift in the technical roadmap: the traditional Moore’s Law relies on shrinking the physical geometric size of transistors (requiring more advanced lithography techniques); the Tau scaling law instead focuses on “time-domain” signal optimization, by reducing resistive and capacitive load on signal propagation to improve effective transistor density, sidestepping reliance on more advanced lithography machines.
LogicFolding is the physical implementation framework of the Tau scaling law, folding and stacking logic circuits into a dual-layer framework to shorten internal interconnect lengths, thereby improving both power efficiency and transistor density. Huawei’s quantified targets: a 55% increase in transistor density and a 41% improvement in power efficiency; in 2026, the Kirin chip’s transistor density is expected to reach 238 MTr/mm². Notably, these figures come from Huawei’s internal statements and have not yet been independently verified through third-party benchmark testing.
NVIDIA’s confirmed competitive advantages and remaining challenges
NVIDIA’s confirmed competitive advantages: the CUDA software ecosystem is currently the industry standard for AI model training, with extremely high developer switching costs; TSMC’s 3nm manufacturing partnership ensures the current most advanced hardware performance; the large-scale deployment plan for Vera CPU systems by hyperscale cloud providers such as Oracle Cloud Infrastructure has been confirmed; analyst Chris Rossbach of J Stern said: “This chipmaker’s leadership in the AI space is unmatched, because unlike cash-strapped competitors, it has the resources to surpass them.”
The known challenges Huawei still needs to address: no independent benchmark results validating performance in large-scale AI training environments; scaling up manufacturing yield rates (Yield Rate) remains uncertain; system-level validation for thermal management, power efficiency, and memory integration solutions is still lacking; the timeline for integrating the Ascend AI chips is 2030, still 4 years away.
Common questions
Why can the Tau scaling law bypass the technical barrier of EUV lithography?
EUV (extreme ultraviolet lithography) is the necessary equipment for manufacturing advanced chips below 7nm. Dutch ASML holds a monopoly on supply, and U.S. sanctions have prevented Huawei from obtaining such equipment since 2019. The key of the Tau scaling law is that it does not improve performance by shrinking the physical size of transistors (which would require shorter-wavelength lithography techniques); instead, it improves signal propagation efficiency and effective transistor density through 3D stacking and shortening internal interconnects (the LogicFolding architecture). In theory, this technical route can achieve higher effective density on currently accessible manufacturing processes in China (such as SMIC’s 7nm), bypassing the direct need for more advanced lithography equipment.
How does this release echo the narrative of last year’s DeepSeek incident?
Both DeepSeek and the Tau scaling law challenge the West’s core assumption that “advanced AI capabilities require high-cost, scarce hardware.” DeepSeek demonstrated that AI model performance at the same level as OpenAI can be achieved with lower compute-cost; the Tau scaling law claims it can achieve high-density chips without relying on sanctioned advanced hardware. Both events directly attack the “compute scarcity premium” logic behind NVIDIA’s valuation and have triggered the market to re-evaluate how much of that scarcity premium is already embedded in NVIDIA’s current stock price.
How will NVIDIA’s 2026 Rubin architecture and Blackwell architecture address potential Chinese competition?
NVIDIA’s hardware roadmap for 2026 has been confirmed: the data center Rubin architecture (R100 GPU + Vera CPU) uses TSMC’s most advanced process and is planned for mass production; the Blackwell-based RTX 50 series for consumer and workstation segments continues to roll out. Oracle Cloud Infrastructure has confirmed a large-scale deployment plan for Vera CPU systems. NVIDIA’s software moat (the CUDA ecosystem) makes its leading position in the global AI training infrastructure market difficult to be directly shaken by hardware-level competition in the short term, especially in markets outside China. Even if Huawei’s technology roadmap achieves its plan, its Ascend AI chips’ direct competition with NVIDIA GPUs will still be after 2030.
